1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal-oxide-semiconductor field effect transistor (MOS transistor) in which an epitaxial process is selectively carried out only on a gate region of the MOS transistor.
2. Description of the Related Art
As semiconductor memory devices are highly integrated and operate at a high speed, the size of an active region of a semiconductor substrate in which the semiconductor device is electrically active is reduced. Thus the length of the gate region of the MOS transistor is also decreased in the active region. As the gate region of the MOS transistor is shortened, the source or drain region has a significant effect on electrical field or voltage of a channel region in the MOS transistor, which is referred to as a short channel effect such as a reduction of threshold voltage in the MOS transistor. That is, as the gate region of the MOS transistor is shortened, channel size is greatly influenced by electrons of the depletion area. The channel size is also greatly influenced by the electrical field and voltage of the source/drain of the MOS transistor as well as by the gate voltage, which may cause the short channel effect such as the reduction of the threshold voltage.
In addition, as the drain voltage is increased, the depletion area of the drain region is increased in proportion thereto, and finally reaches the source region of the MOS transistor. Therefore, when the length of the gate region becomes short, the depletion areas of the source/drain regions are interconnected with each other. When the source depletion area is connected to the drain depletion area, the electrical field of the drain region reduces the voltage of the source region, thus an electrical current passes between the source and drain regions even though the channel is not formed therebetween, which is referred to as a punch through phenomenon. When the punch through phenomenon occurs, the drain current is not saturated, rather rapidly increased even in the saturation region.
In general, the deeper the junction depth of the source/drain regions is, the more the short channel effect is generated. Therefore, a parasitic resistance of the source/drain regions such as a sheet resistance or a contact resistance needs to be reduced while the junction depth of the source/drain regions shallows in order to prevent the short channel effect. A silicidation process is widely used for reducing a specific resistance of the gate electrode and a parasitic resistance of the source/drain regions. According to the silicidation process, the metal silicide layer is selectively coated on a surface of the gate electrode or of the source/drain regions.
However, the above recent trend of reducing the size of the gate electrode such as a thickness thereof causes various problems during the silicidation process. For example, the silicide layer is agglomerated along a grain boundary of the gate electrode, or the gate insulation layer and the active region are attacked by the silicide layer on the gate electrode in case of a small thickness of the gate electrode.
An elevated MOS transistor including an elevated source/drain structure has been introduced for obviating the above-described problems. In the elevated MOS transistor, the source/drain region is elevated and extends above the substrate by a silicon epitaxial layer coated thereon through a selective epitaxial growth (SEG) process. A method of manufacturing the elevated MOS transistor is disclosed in Korean Patent Laid Open Publication No. 2003-56932.
FIGS. 1A and 1B are schematic cross-sectional views illustrating the method of manufacturing a semiconductor device disclosed in the above Korean Patent Laid Open Publication.
Referring to FIG. 1A, a gate insulation layer 12 and a gate electrode 14 including polysilicon are sequentially coated on a substrate 10, and ions are lightly implanted on a surface portion of the substrate 10 adjacent to the gate electrode 14 to thereby form lightly doped source/drain region (not shown).
A first insulation layer including a silicon oxide layer and a second insulation layer including a silicon nitride layer are sequentially formed on a surface of the substrate 10 including the gate electrode 14. Then, the first and second insulation layers are anisotropically etched, so that a first insulation layer pattern 18 and a second insulation layer pattern 20 are formed along side surface of the gate electrode 14. For example, the first and second insulation layer patterns 18 and 20 are provided as a gate spacer 22.
Other ions are heavily implanted on a surface portion of the substrate 10 adjacent to the gate electrode 14 using the gate electrode 14 and the gate spacer 22 as an ion implantation mask to thereby form a heavily-doped source/drain region (not shown).
The silicon epitaxial layers 24a and 24b are grown on a top surface of both the gate electrode 14 and the source/drain regions.
Referring to FIG. 1B, the silicon epitaxial layers 24a and 24b are silicidated, and the gate silicide layer 26a and source/drain silicide layer 26b are formed on the gate electrode 14 and on the source/drain regions, respectively.
The elevated MOS transistor manufactured according to the above Korean Patent Laid Open Publication is advantageous in that both the gate electrode and the source/drain regions are elevated by the SEG process, and the electrical resistance of the gate electrode 14 and the source/drain regions is reduced by silicidation of the silicon epitaxial layer.
However, the elevated MOS transistor according to the above Korean Patent Laid Open Publication has some disadvantages. For example, since the elevated source/drain regions and the gate electrode 14 come into indirect contact with each other through the medium of the gate spacer 22, a parasitic capacitance A is generated between the gate electrode 14 and the elevated source/drain regions proportional to a dielectric constant of the gate spacer 22. The parasitic capacitance A degrades the capability of the transistor for controlling threshold voltage, thus causing unnecessary power consumption.
In addition, since the silicon epitaxial layer is grown along a predetermined direction on the silicon substrate 10, a thickness of a peripheral portion of the silicon epitaxial layer 24b adjacent to the first insulation layer pattern 18 is decreased, so that a facet is formed on the peripheral portion of the silicon epitaxial layer 24b. Accordingly, an implantation profile is distorted around the facet after the dopants are implanted onto the source/drain region on which the silicon epitaxial layer is already grown. The implantation profile is formed abnormally deep into the silicon substrate 10 around the first insulation layer pattern 18, thereby forming a distortion implantation profile, so that intensity of the electric field becomes very high at a portion of the silicon substrate 10 corresponding to the distortion implantation profile, and a leak current is generated from the silicon substrate 10.